package bus

import chisel3._
import chisel3.util._
import utils._


class CBus32ToAHBL64(conf : AhbConfig) extends Module {
    val io = IO(new Bundle{
        val in  = Flipped(new CBus32Bundle(32, 32))
        val out = new AhbBundle(conf)
        val clk2en = Input(Bool())
    })

    val cbus32To64 = Module(new CBus32To64())
    val cbus64ToAhbl64 = Module(new CBus64ToAHBL64(conf))

    cbus32To64.io.clk2en := io.clk2en
    cbus32To64.io.in <> io.in

    cbus64ToAhbl64.io.clk2en := io.clk2en
    cbus64ToAhbl64.io.in <> cbus32To64.io.out

    io.out <> cbus64ToAhbl64.io.out
}